1. Field of the Invention
The present invention relates to a digital-to-analog converter (DAC) and a device related to SRAM, and especially relates to a noise-equalized DAC and a device capable of equalizing noise in SRAM.
2. Description of the Related Art
When mixed signal integrated circuits, comprising analog circuits and digital circuits, are developed, how to process noise is an important subject, especially in highly integrated circuits.
For example, in a mixed signal image processing integrated circuits on a chip or on a application board comprising an ADC, DAC and SRAM, the DAC and SRAM may affect the sampling level of the ADC. This may cause static having a different grade level compared with its neighborhood.
The following statements describe how an ADC is affected by the DAC and the SRAM.
(1) How DAC affects the sampling level of an ADC
When the ADC is sampling image data, if the DAC receives a BLANK signal at this moment, the DAC must make the whole screen black. A non-equalization noise burst occurs at the same time as each horizontal line. This non-qualization noise burst affects the sampling level of the DC through the noise path and causes static having a different grade level compared with its neighborhood.
Now refer to FIG. 1A which shows a DAC timing sequence chart for each horizontal line. During time period C to F, the ADC converts analog signals into digital signals. The DAC works in time period B to D and time period E to G. In time period D to E, the current source of the DAC is forced into a sleep state due to a high voltage state of BLANK signal. At the edge of the high voltage state of BLANK signal, a large transient current, originally occurring in the DAC, does not flow to the GND terminal. This sudden change in transient current causes a non-equalized noise burst.
FIG. 1B shows a structural diagram of a conventional DAC. As shown in FIG. 1B, a DAC comprises a thermal code decoder 10, a plurality of D-type flip-flops 20, a plurality of preprocessors 30, and a plurality of current sources 40.
FIG. 1C is a circuit diagram of the current source of a DAC of the prior art. Transistor P1 supplies a fixed current. Transistor P2 controls the current source in a sleep state when the BLANK signal is high. Transistors P3 and P4 receive signals DA and DA.sub.-- BAR through their gates, wherein the signal DA.sub.-- BAR is an inverted signal of signal DA. When the signal DA is "0," the transistor P4 is ON, and the transistor P3 is OFF. Conversely, when the signal DA is "1," the transistor P4 is OFF, and the transistor P3 is ON. When the BLANK signal arrives, the transistor P2 is turned off and turns off the current source. Therefore, a non-equalization noise burst occurs.
FIG. 2 is a simulation result for the transient current of the DAC. In FIG. 2, I27 represents the current flowing through the transistor P3 of FIG. 1C and the signal OUT is the voltage at terminal out of FIG. 1C. When the BLANK signal is high, the screen becomes black because of the voltage of OUT is 0V and the current signal I27 is turn to 0 mA simultaneously.
Because the DAC randomly converts image data, the non-equalization noise burst occurs randomly. When the image data at edge of the BLANK signal has a darker hue, the non-equalization noise is more intense, and vice versa.
Since a screen consists of hundreds of horizontal lines, some fixed regions of the screen may have a different grade level compared with adjacent area.
When the hue of image data is lighter, the transient current at GND terminal (VSS.sub.-- DAA in FIG. 1C) is smaller, and a smaller change in transient current occurs in case of a high BLANK signal, and vice versa.
(2) How SRAM affects the sampling level of an ADC
Now refer to FIG. 3A, which is a timing sequence chart of a mixed image processing IC which comprises an ADC and SRAM. In FIG. 3A, signal RE and WE represent a read and write operation of SRAM, respectively. The signals RCLK and WCLK represent read and write clocks, respectively. The signal ADC represents the operation period of the ADC circuit. As shown in FIG. 3A, the ADC circuit converts analog signals into digital signals in time period C to F. However, the SRAM only executes a write operation in time period D to E, and executes both read and write operations in time period C to D and period E to F. Therefore, read/write operations are not uniform in time period D to E. From simulations of transient currents, it is known when the read/write operations are not uniform in one period, the transient current becomes smaller and a non-equalization noise burst will occur.
FIG. 3B is a block diagram of applying SRAM for read/write operations of the prior art. In FIG. 3B, RADDR0 and RADDRn represent the LSB (least significant bit) and MSB (most significant bit) of the reading address, respectively. The signal R.sub.-- RESET and W.sub.-- RESET are used to reset the read and write counter respectively.
Therefore, there is a need to improve upon the disadvantages of the prior art.